Field of Invention
The present invention relates generally to Integrated Circuits (ICs), such as System on Chips (SOC) with on chip processors, and more particularly with programmable logic accelerators embedded or coupled with SOC.
Description of Related Art
Systems on Chips (SOC) are often selected by design engineers to provide flexible and powerful solutions for many applications. Processors can run user software and provide required flexibility. Dedicated logic accelerator blocks implement SOC application logic using Application Specific Integrated Circuit (ASIC) technology. These dedicated accelerator blocks provide high performance required by the application, which a software solution cannot provide. Input and Outputs (IO) to the SOC are handled by special IO blocks. Conventional SOCs are implemented using multiple processors, memory, logic and IO blocks that interact with each other using SOC interface buses. Operating System (OS) software running on processors manage and coordinate the functionality of the SOC. OS also runs and control application software.
In another conventional structure, logic can also be made programmable by using Field Programmable Gate Arrays (FPGA) in an SOC solution. FPGAs are built using Configurable Logic Blocks (CLB) that can be programmed to implement required logic functionality. FPGAs provide more performance than processors and can be used where user needs logic configurability. FPGAs are more expensive than ASIC design blocks. At the cost of area and power, FPGAs provide more flexibility than ASIC design blocks. In these conventional structures, FPGA cannot implement larger logic blocks that require more logic than present in selected FPGA. In many cases, FPGAs are not integrated with SOC architecture to use OS in an efficient way.
Accordingly, it is desirable to have a Programmable Logic Accelerator (PLA) that provides the required flexibility and performance. The resources available do not limit the implementation on PLA. PLA integrates natively with OS to utilize the memory and resource management infrastructures of SOC.